A fast settling multi-standard CMOS fractional-N frequency synthesizer for DECT, GSM, CDMA and NADC wireless communication standards is proposed. This frequency synthesizer was simulated with ADS2008 in TSMC RF CMOS 0. 18 µ m. Frequency range is 824-1900 MHz, a switched capacitor LC-VCO was used in order to produce this frequency range. Frequency synthesizers have three main specifications of phase noise, settling time and power consumption. A new channel select circuit was designed instead of ∑ ∆ modulator to locate spur tones far from center frequency. A high reference frequency was used in order to reduce the VCO phase noise and locate the spur tones far from center frequency; these tones are produced by charge pump (reference spur) and N/N+1 divider (fractional spur). Two ways were used for phase noise optimization; in the first way phase noise was reduced by a low pass filter and a bypass capacitor (CT) that eliminate thermal noise and 2ω 0 harmonics of tail current source; in the second way with biasing of VCO transistors only in saturation region preventing reduction of quality factor(Q) in tank circuit. These two ways in VCO of DECT were used, consequently the phase noise at 1875MHz center frequency was improved from-119. 4 dBc/Hz at 3. 4 MHz offset frequency to-144. 3 dBc/Hz at 3. 4 MHz offset frequency. The settling time for all standards was achieved less than almost 1 μ s over the entire frequency range. For DECT synthesizer phase noise of-116. 37 dBc/Hz at 3 MHz offset frequency was obtained, the first spur tone was located in 7. 35 MHz offset from center frequency, also settling time of 350ns was obtained. The whole frequency synthesizer in loop1 (for DECT) draws 13 mA and in loop2 (for GSM900, CDMA & NADC) draws 13. 67 mA from a 1. 8 V voltage supply.

To achieve a low reference spur for an Integer-N frequency synthesizer, a new spur reducing technique was proposed. To reduce the size of periodic ripples on the VCO control voltage, the low pass filter, and the charge pump were added with a spur reduction system. By lowering the amplitude of the periodic ripple on the VCO control voltage, we managed to lower the reference spur. The introduced technique removes the necessity to decrease bandwidth and CVO gain reference spur suppressing. To demonstrate the effectiveness of the proposed structure, a 2. 06 – 2. 22 GHz frequency synthesizer was used and the 180-nm CMOS technology was used for post-layout simulation. The proposed frequency synthesizer represents the reference spur of-85. 84 dBc at 20 MHz offset and phase noise of-108dBc/Hz at 200 kHz offset frequency also it is locked after 2. 8us while occupied 0. 35 mm2 of the chip area.

This paper presents system-level design and implementation of an ultra-wide tunable, high precision, fast locking, low phase noise, and low power portable fractional-N frequency synthesizer. The output frequency of the proposed design is ranged from 54 MHz to 6.8 GHz. The VCO cores cover frequencies from 3.4 GHz to 6.8 GHz. The programmable output dividers allow generation of the lower frequencies. The output power is tunable between -4dBm and+5dBm. It can generate a wide range, high precision, and linear frequency sweep. The sweep rate, frequency step, and frequency range are tunable. The new frequency tuning algorithm, named Yas algorithm, is proposed to improve frequency precision of the synthesizer. To demonstrate the efficiency of the Yas algorithm, the results of MATLAB simulations and experimental measurements are presented. The output phase noise is -95.55 dBc/Hz at 1 KHz offset from 3 GHz. The experimental measurement results demonstrate that the implemented frequency synthesizer can be used for applications, such as oscillator of spectrum analyzer, automatic test equipment, FMCW radars, high-performance clock source for high speed data converter, satellite communications, and measurement systems.

This paper presents a modified 32-bit ROM-based Direct Digital Frequency Synthesizer (DDFS). Maximum output frequency of the DDFS is limited by the structure of the accumulator used in the DDFS architecture. The hierarchical pipeline accumulator (HPA) presented in this paper has less propagation delay time rather than the conventional structures. Therefore, it results in both higher maximum operating frequency and higher maximum output frequency. Ripple Carry Adder (RCA) is used at each stage of Conventional pipeline accumulators, whereas the modified pipeline technique contains Carry Look-ahead Adder (CLA) instead of RCA. The proposed method consists of hierarchical adders that have three parts, two blocks of 4-bit CLA and a separated block to estimate carry bits independently. To reach a better frequency resolution in the DDFS, larger phase accumulator is needed. Moreover, in conventional DDFSs, as the number of phase bits increases, to have non-truncated phase mapping, huge amount of memory will be needed. The trigonometric relations of the sine and the cosine functions are used in the phase mapping technique proposed by Symon in order to reduce the size of the Look Up Table (LUT). The method applied in this work combines quarter wave symmetry of the sine samples, the phase difference between the sine and the cosine samples and trigonometric relations of the sine and the cosine functions to reduce the total memory size. The SFDR of the output wave will remain approximately constant (132 dBc) in comparison with the previous works. Finally, the proposed architecture is simulated on Stratix II FPGA. This structure has the frequency range of 0 to 245 MHz with 0.05 Hertz frequency resolution.

This paper analyzes the phase noise of the single loop second-order frequency fractional-N synthesizer. The aim of this paper is the reduction of the output phase noise in the application of commercial and military subsystems as well as general local oscillators. The mathematical model of PLL based frequency synthesizer is analyzed to develop the minimum phase noise in the specific frequency range. An exact closed form relationship between bandwidth and output phase noise of the frequency synthesizer as well as the bandwidth-phase noise diagram is extracted by using this closed form relationship. From the analysis and simulation results, we observe that the system has minimum phase noise at a particular closed-loop bandwidth. To validate simulation results, the synthesizer is implemented on the low loss professional printed circuit board (PCB). Measurement setup is scheduled on spectrum analyzer 8562A in the span of 5MHz and 10MHz. These measurements show excellent results in output spectrum of the frequency synthesizer.

This paper presents the design and simulation of a high-performance fractional-N phase-locked loop (PLL) frequency synthesizer with a 60 kHz bandwidth, operating within a frequency range of 2.4 GHz to 2.5 GHz. The design integrates advanced features such as a sigma-delta modulator configured in a 1-1-1 MASH architecture and a fractional divider, both implemented with intelligent control circuits to precisely determine the division ratio. These innovations aim to reduce delay and power consumption while enhancing phase noise performance and ensuring robust system stability. The fractional divider is a critical component of the PLL, enabling frequency division into fractional values with high precision. By incorporating intelligent control circuits, the design achieves accurate adjustments to the division ratio, contributing significantly to the overall reliability and efficiency of the PLL. Additionally, integrating advanced modulation and filtering techniques further optimizes the loop's performance by suppressing unwanted noise and ensuring stability under varying conditions. Simulation results demonstrate the effectiveness of the proposed design, achieving a fast frequency lock time of approximately 3 µs, a stable phase margin of 45 degrees, and an impressive phase noise performance of -148.13 dBc/Hz at a 1 MHz offset. Furthermore, the system's total power consumption is only 2.36 mW, highlighting its exceptional balance between power efficiency and high performance.